Job Description
Job Id:
JPS-2055
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Job description
- Plan develop and implement comprehensive testbenches in SystemVerilog to validate RTL module functionality across various scenarios
- Execute testbenches consistently identifying and documenting potential issues and bugs discovered during simulation
- Perform RTL simulations using tools like ModelSim or QuestaSim to verify design accuracy and troubleshoot errors
- Interpret and analyze state machine and module implementations from RTL code to identify various scenarios for targeted testing
- Utilize shellbash scripting to streamline and automate the test execution process enhancing workflow efficiency
- Conduct detailed RTL code reviews in alignment with model diagrams offering constructive feedback to improve design fidelity
- Actively participate in design review meetings contributing insights and recommendations to ensure robust design architecture
